latch circuit
英 [lætʃ ˈsɜːkɪt]
美 [lætʃ ˈsɜːrkɪt]
网络 锁存电路; 闩锁电路; 锁定电路; 栓锁电路; 锁电路
双语例句
- The threshold detector is similar to a Schmitt Trigger in that it is a latch circuit with a large dead zone.
阈值检测器就是一种回差范围较大的锁存电路，与施密特触发器相似。 - We also use EPLD programmable logic device to implement the counter, flip latch, and control logic circuit, largely simplifying the circuit implementation. The simulating result is presented too.
使用可编程逻辑器件EPLD实现了计数、锁存、控制等数字电路，大大简化了硬件电路，给出了仿真模拟调试结果。 - In the design, a host of theories and design methods must be studied, such as mismatch, symmetrical switch, latch, current source, bias circuit, layout and so on.
在DAC的设计过程中，需要对失配、对称开关、锁存、电流源、偏置电路、分段等诸多理论和设计方法进行探讨。 - The design of LED display screen by means of dynamic scanning is introduced. The display principle and date latch of display screen and interface circuit of driver as well as application program chart are given.
本文设计了一种采用单片机动态扫描控制的LED图文显示屏，文中给出了显示原理，显示屏的数据锁存、驱动接口电路、以及应用程序框图。 - Based on the preamplifier-latch fast-compare theory, a novel topology of CMOS preamplifier latch comparator circuit is presented.
基于预放大锁存快速比较理论，提出了一种新型高速低功耗CMOS比较器的电路拓扑。 - Cipher-lock consists of R-S latch; this paper introduced electric circuit design and working principle of light touched eipher-lock.
本文介绍由R-S锁存器组成的轻触式数字密码锁的电路设计及工作原理。 - A decoder circuit, a encoder circuit and a latch circuit are also designed, and parts of layout are realized.
设计了数字译码电路、编码电路和锁存器电路，并进行了部分版图设计。 - It consists of a Boxcar integrator, a latch, a pulse-width modulatior and a signal control circuit.
它由Boxcar积分器，锁存器，脉冲宽度调制器和控制信号电路组成。 - It consists of direction distinguishing circuit, up/ down counting circuit, output buffer circuit, input latch circuit, decode and control circuit, F/ V converting circuit.
它主要由方向判别电路、双脉冲加减计数电路、输出缓冲电路、预置锁存电路、译码控制电路、F/V转换电路等组成。 - A novel high-speed and low-voltage latch is used to realize the core circuit cell.
核心电路单元采用一种新的高速、低电压锁存器结构实现。 - Based on preamplifier-latch theory, a topology structure of CMOS positive feedback comparator circuit with preamplifier is presented, and methods to improve transmit delay time, kick-back noise and input offset voltage of the circuit are described.
基于预放大-锁存理论，提出了一种带1级预放大器的高速CMOS锁存比较器电路拓扑结构；阐述了其传输延迟时间、回馈噪声和输入失调电压的改进方法。 - Design of Foolproof Key-press Latch and Decoding Circuit
防误操作的按键锁存、译码电路的设计 - Feedforword summation and local feedback are implemented in capacitor network. 1-bit quantizer is realized by a dynamic comparator with latch. Cascaded integrators have non-inverting input. The whole circuit is controlled by non-overlapping clock signals.
前馈求和电路和局部反馈支路通过电容网络实现，一位量化器通过带锁存功能的动态比较器实现，级联积分器采用输入非反相的积分结构，整体电路由两相不交叠时钟控制。 - Finally, some of the sub circuits witch the author designed are analyzed. Including noises of power supply insulation, states latch circuit, oscillator with frequency jitter and current limiter.
最后，分析和介绍了芯片中的部分子电路，包括：电源噪声隔离电路、基准电压源启动前的状态锁定电路、带频率抖动的振荡器和限流电路。 - The synchronized switching contorl signals by added the specific latch circuit. The latch also can decrease glitch power and get the better dynamic performance.
采用锁存器来同步电流源开关控制信号，同时降低毛刺，改善了动态性能。